The push to sub-0.18 micron multilevel metallized interconnections, such as lines, via, and trenches, and the desire to produce faster semiconductor devices, has resulted in a shift toward the use of copper for making electrical interconnections in ultra-large scale integration circuits. The deposition of copper interconnects are not without difficulties, however. For example, when copper is etched, it tends to be redeposited elsewhere on the semiconductor device, or on the processing chamber. Copper atoms also readily diffuse into silicon-containing dielectric layers. The contamination by copper in unwanted locations can degrade or destroy the performance of active devices in integrated circuits. One approach to reducing the problems with copper etching and diffusion, is the deposition of an underlying barrier layer to block the migration of copper atoms into other components of the semiconductor. To facilitate the adhesion of copper to the diffusion barrier, a seed layer of copper is deposited over the diffusion barrier, followed by the deposition of a second thicker copper conducting layer over the copper seed layer.
Typically, the copper seed layer is deposited on a semiconductor wafer by a vacuum process, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thick copper conducting layer is deposited by a wet process, such as electrochemical deposition (ECD). Because the deposit of the seed layer and thick conducting layer involve two distinct processes and tools, the wafer has to be removed from the copper seed layer depositing tool, exposed to the atmosphere for a period, and then placed in the tool for depositing the thick layer. Backlogs and mismatches in the machine times for seed layer and thick layer deposition can extend the time window where the wafer is exposed to the atmosphere to several hours.
During this time window, the surface of the seed layer surface oxidizes. In addition, atmospheric molecular contaminants (AMCs) containing hydrocarbons can form on the seed layer. The presence of irregular oxide or AMCs deposits on the copper seed layer can result in thinning or dissolution of the copper seed layer when placed in acidic electroplating solutions used for ECD. The resulting discontinuities in the seed layer exacerbate the formation of voids in the thick conducting layer during electroplating, thereby negatively impacting device performance and reliability. In addition, the oxide deposits may not be fully removed during ECD. The continued presence of an oxide deposits between the seed layer and the thick conducting layer weakens adhesion between these layers, making the interconnection more prone to mechanical failure. The current practice is to therefore minimize copper oxidation and organic compound contamination by restricting the period (e.g., a maximum of about 2 hours) between depositing the seed layer and thicker conducting layer by ECD processes. This approach, however can still result in unacceptably high oxidation and increased cycle times and therefore increased costs.
Previous approaches to mitigate copper oxidation and AMCs are imperfect, because there can still be defective devices with degraded device performance generated or increased costs for device manufacture. One approach is to store the partially completed semiconductor wafers having the seed layer in a holding room whose air is filtered of AMCs. Maintaining a holding room is expensive, however, and does not prevent oxidation. Another approach has been to store the partially completed semiconductor wafers in a nitrogen-purged box. This is also a costly solution and results in additional logistical cost. Still another approach is to clean the copper seed layer with sulphuric acid prior to ECD. Pre-cleaning with sulphuric acid, however, also can etch away the copper seed layer at an undesirably high rate (e.g., over 4 nm/min). This can cause the total removal of the portions of the copper seed layer which, in turn, results in defective devices. Moreover, if the time window were to unexpectedly increase, for instance, due to the lack of availability of the ECD tool, then sulphuric acid pre-cleaning would not likely be repeated out of concern that the copper seed layer would be entirely removed.
Accordingly, what is needed in the art is a method of making copper interconnections that do not exhibit the limitations of the prior art.